Redundancy in a memory system is used to provide replacement memory cells for defective, or damaged, memory cells. The storage capacities of EEPROM and flash memories are being made larger to meet increasing memory requirements. Typically, EEPROM and flash memory devices are available in a single chip or single integrated circuit package configuration. A typical memory device integrated circuit package contains a memory array and a number of other circuits, including a memory controller or microcontroller and various other circuits that are used, for example, to address, program, and erase memory cells within the memory array.
Traditionally, replacement of defective memory cells with various redundancy schemes has been done in the memory chip itself close to the column (COL) and row (ROW) address decoding circuitry.
U.S. Pat. No. 6,760,255 to Conley et al. describes a non-volatile memory system in which a memory controller manages redundancy across multiple memory chips. Memory device defect data are discovered during manufacturing processes and are stored as a single record of information for each memory chip. The memory controller has access to this information and uses the defect data to redirect storage of user data around defective memory and into alternate locations.
U.S. Pat. No. 5,084,838 to Kajimoto et al. describes a plurality of memory integrated circuits mounted on a large-scale integrated circuit capable of coupling the memory circuits together. A plurality of redundant memory devices is incorporated to replace defective memory circuits. A redundant memory controller, a separate device, is used to monitor low-order address bits and coordinate use of redundant rows or columns to replace the corresponding locations in the defective memory circuits. The redundant memory controller uses previously stored alternate memory addresses to remap memory access at defective locations. Although the controller and memory circuits are integrated at a wafer level, operationally they are separate devices.
U.S. Pat. No. 5,764,574 to Nevill et al. describes a method and apparatus for independent redundancy programming of individual components of a multiple-component semiconductor device. A multiple-chip memory module includes a plurality of memory devices each having redundant circuitry for backend repair of defective memory cells. The redundant rows or columns are incorporated when a predetermined combination of programming signals are applied to specific terminals of the redundant device. A particular set of signal routing allows a separate device to manage substitution of redundant memory circuitry. In this way redundancy is incorporated across a memory system formed by a multiple device assembly.
The drawbacks of the prior art approach to having on-chip redundancy circuitry for larger and larger memories include increasing complexity and manufacturing costs for that extra circuitry. For certain memory structures, it is desirable to reduce or minimize control logic or control circuits that are located on the memory device chip. It is also desirable to minimize the number of memory pins used for interfacing with a host interface circuit.